The present invention relates to a method for fabricating semiconductor circuits containing both DRAM and logic cells. In particular, the invention relates to fabricating semiconductor circuits containing vertical pass gate embedded DRAM (EDRAM) arrays and dual workfunction logic gates.
With the advent of Large Scale Integration (LSI), many integrated circuit designs include several circuit functions on a single semiconductor substrate, such as memory storage and logic functions for addressing and accessing the memory. In the case where a logic region and a DRAM cell (memory) region are formed on the same substrate, the circuitry is commonly referred to as an embedded DRAM. The integration of logic and memory regions improves overall device performance by decreasing communication delays between memory devices on one chip and logic devices located on a second chip. In addition to the improvements in device performance, processing costs for integrating memory and logic circuit functions on the same semiconductor substrate potentially could be reduced due to the sharing of specific processing steps used to fabricate both types of devices. Present trends in DRAM technology are driving towards continued scaling of minimum feature size (F) in the DRAM array, and more compact cell layouts (e.g., 7F2, 6F2, etc.). As a result, the above noted problems in the prior art become even more problematic, especially for devices where F=100 nm and smaller.
DRAM circuits will usually include an array of memory cells interconnected by rows and columns, which are known as wordlines and bitlines, respectively. Reading data from, or writing data to the memory cells is achieved by activating selected wordlines and bitlines. Typically, the DRAM memory cell comprises a MOSFET (metal oxide semiconductor field effect transistor) connected to a capacitor. The MOSFET generally includes a gate region and diffusion regions. The diffusion regions, depending on the operation of the transistor, are often referred to as either drain or source regions.
There are different types of MOSFETs. Trench-gated MOSFETs are a class of MOSFETs in which the gate is positioned in a trench that is formed at the surface and extends into the silicon. The gate is formed in a lattice-like geometric pattern which defines individual cells of the DRAM; the pattern normally taking the form of closed polygons (squares, hexagons, etc.) or a series of interdigitated stripes or rectangles. The current flows in vertical channels which are formed adjacent to the sides of the trenches. The trenches are filled with a conductive gate material, typically doped polysilicon, which is insulated from the silicon by a dielectric layer normally consisting of silicon dioxide.
The trench-gated MOSFETs are normally formed by etching trenches of various dimensions into a silicon substrate. The gate trenches normally extend into the substrate and are frequently rectangular, with flat bottoms bounded by corners. Trenches commonly contain storage capacitors below the MOSFETs and have N+ doped polysilicon as one plate of the capacitor (a storage node). The other plate of the capacitor is formed usually by diffusing N+ dopants out from a dopant source into a portion of the substrate surrounding the lower part of the trench. Between these two plates a dielectric layer is placed which thereby forms the capacitor.
Typically, isolation regions are formed in the substrate to prevent carriers from traveling through the substrate between adjacent devices. The isolation regions are generally thick field oxide regions extending below the surface of the semiconductor substrate. One such technique for forming the isolation region is the local oxidation of silicon, i.e., LOCOS regions. LOCOS field oxidation regions are formed by first depositing a layer of silicon nitride on the substrate surface and then selectively etching a portion of the silicon nitride layer to form a mask exposing the substrate where the field oxidation will be formed. The masked substrate is then placed in an oxidation environment and a thick layer of oxide is selectively grown in the exposed mask regions forming an oxide layer extending above and below the substrate surface. An preferred alternative to LOCOS field oxidation is the formation of shallow trench isolation regions in contemporary CMOS technology, commonly referred to by those in the art as an STI region. In the process of forming the STI regions, a deep trench is formed in the semiconductor substrate by, for example, anisotropic etching. The trench is then filled with oxide back to the surface of the substrate to provide an isolation region between adjacent devices.
In a typical DRAM array, the wordlines need to be capped with an insulator to allow formation of borderless diffusion contacts, whereas in the logic supports the gate conductors must be exposed to allow the introduction of dual workfunction doping and silicidation. Silicided gates and source/drain regions greatly complicate the processes for forming array MOSFETs since the array MOSFETs need bitline contacts which are borderless to adjacent wordline conductors. In addition, it has been found that silicide junctions in the array frequently result in increased current leakage of the memory device. Conventional solutions to these integration problems require additional masking steps to remove the insulating gate cap from the support MOSFETs prior to the silicidation process.
Problems encountered in the formation of vertical pass gate embedded DRAM (EDRAM) arrays and dual workfunction logic gates include the lithography steps used to simultaneously form the support gates and wordlines. The wordlines used in the array have tight pitch requirements whereas the support regions have relatively relaxed pitch features. Lithographic patterning these different pitches typically requires complex solutions, such as alternating phase shift masking techniques and the like, to overcome these difficulties. It is desirable to have the pitch requirements for the array and supports be similar or more relaxed to overcome these well known lithographic problems. However, this is not currently feasible as circuitry density increases and as such, common practice is to separately pattern the array and supports.
Another problem with prior art processes is in the formation of the local interconnects. Conventionally, one of the metallization layers is used for forming both the bitline and the local interconnects. It is preferred to have a simpler process that eliminates the metallization layer and its attendant processing to form the local interconnect and metal layer. U.S. patent application Ser. No. 09/725,412 to Mandelman et al. filed on Nov. 29, 2000 shows how to form dual work function logic gates with vertical DRAM cells using a raised shallow trench isolation (RSTI) process. This process has the disadvantage that the support logic devices are subject to the thermal processes of the shallow trench isolation which can degrade the well profile.
U.S. patent application Ser. No. 09/706,492 to Mandelman et al. filed on Nov. 3, 2000 overcomes many of the above noted thermal problems. The process disclosed therein generally includes a) patterning only the array gate wiring for the vertical transistors; b) forming silicided bitlines and peripheral transistors concurrently and c) showing a metal to form local interconnects. However, this methodology becomes difficult to implement for tight array pitches patterned with 193 nm lithography.
Accordingly, there is a need for improved processes that address these concerns and provide a process that can be used for the more compact cell layouts.
A process and structure for producing high density embedded DRAM and logic structures is described. The process includes fabricating embedded vertical DRAM arrays with a silicided bitline and a polysilicon interconnect. In one embodiment, the method of forming a memory array and support transistors on a semiconductor substrate comprises providing a substrate including a memory structure having an array region and a support region separated by an isolation region, wherein the array region includes a plurality of dynamic random access memory cells embedded in the substrate, wherein adjacent dynamic random access memory cell are connected to each other through bitline diffusion regions, and wherein the memory structure is capped with a top oxide layer; applying a block mask to protect the array region while stripping the top oxide layer from the support region; forming support implants, forming a support gate oxide layer and patterning a first polysilicon layer onto the support gate oxide layer; forming a tungsten nitride, tantalum nitride or titanium nitride layer on all exposed surfaces of the substrate; forming a conductive metal layer on the nitride layer; forming an insulating layer on the conductive metal layer; removing portions of the conductive nitride layer, the conductive metal layer and the dielectric capping layer from the support region to form a support gate structure, wherein the support gate structure comprises the gate oxide layer, the first polysilicon layer, the conductive nitride layer, the metal layer and the dielectric capping layer, wherein the support gate structure further includes forming an insulated spacer on the sidewall of the gate structure and removing the conductive nitride layer, the conductive layer and the dielectric capping layer structure from the isolation region to define a local interconnect region; forming a protective layer on all exposed surfaces of the substrate; forming an array gate structure in contact with the memory cell and exposing a portion of the bitline by removing portions of the protective layer, the conductive nitride layer, the metal layer and the dielectric capping layer from the array region, and simultaneously removing the protective layer from the isolation region; forming an spacer layer on sidewalls of the array gate structure; depositing a second polysilicon layer onto the substrate; selectively patterning and etching the second polysilicon layer in the isolation region to forma landing pad while removing the polysilicon layer in the support regions; and simultaneously forming silicide layers on an exposed portion of the source and drain regions in the support region, on the second polysilicon layer overlaying the bitline diffusion regions in the array region, and on the second polysilicon layer defining the landing pad.
In another embodiment of the process, the method of forming a memory array and support transistors on a semiconductor substrate includes providing a memory structure having an array region and a support region separated by an isolation region, wherein the array region includes a plurality of dynamic random access memory cells embedded in the substrate, wherein adjacent dynamic random access memory cells are connected to each other through bitline diffusion regions which are capped with a top oxide layer; depositing a barrier layer, a metal layer, and a dielectric capping layer onto the substrate; removing portions of the barrier layer, the polysilicon layer, and the dielectric capping layer from the substrate to form an array gate structure; depositing a layer of nitride onto the substrate and removing the nitride layer from the non-array regions and the top oxide layer in the support region; forming a support sacrificial oxide layer, forming support implants, removing the sacrificial layer and forming a support gate oxide layer; depositing a first layer of polysilicon onto the substrate and etching the first polysilicon layer to the support gate oxide to form a support gate structure; forming spacers on the sidewalls of the array gate structure and support gate structure, wherein the spacer is removed in array regions for forming a bitline contact; depositing a second polysilicon layer and applying a mask to pattern and form a landing pad in the array and gate conductors for the support transistors; siliciding the landing pad, the support gate structure, the support gate conductors and the second polysilicon layer overlying the bitline diffusion regions in the array region.
In another embodiment of the process, a method of forming a memory array and support transistors on a semiconductor substrate includes forming a trench capacitor in a silicon substrate having a gate oxide layer, a polysilicon layer, and a top cap layer deposited thereon; patterning an array gate structure by removing portions of the polysilicon layer and the cap layer; depositing a nitride layer onto the substrate; applying a patterned mask to selectively etch the nitride layer in the support region and isolation region, and forming a sacrificial oxide layer; forming implants in the support region and subsequently stripping the sacrificial oxide layer and forming a gate oxide layer; depositing and patterning a second layer of polysilicon in the support region to the gate oxide layer and the gate cap layer forming the gate stack, and in the array region patterning the second polysilicon layer to the nitride layer; depositing a second layer of nitride onto the substrate and a layer of tetraethylorthosilicate thereon; removing portions of the tetraethylorthosilicate layer in the array region and in a region where a local interconnect is formed; conformally depositing a third layer of polysilicon onto the substrate and planarizing the third polysilicon layer over the gate stack in the support region; patterning the third polysilicon layer to define the local interconnect, and in the support region, further removing the nitride layer and simultaneously forming implants therein and doping the gate stack; and siliciding the exposed portions of the polysilicon layer in the array region and the local interconnect.
A semiconductor device including a dual workfunction support transistor and an embedded DRAM array free of a M0 first metal layer includes a support region comprising a gate structure, a source and a drain region adjacent to the gate structure, and a silicide layer disposed on the source and drain regions, wherein the gate structure comprises a dielectric capping layer, a metal conductor and a polysilicon layer; an array region comprising a plurality of embedded DRAM cells, a bitline diffusion region electrically connecting adjacent DRAM cells, a polysilicon layer and a silicide layer disposed on the polysilicon layer; an isolation region, wherein the isolation region electrically separates the support region from the array region; and an interconnect structure disposed on the isolation region comprising a polysilicon layer and a silicide layer formed on the polysilicon layer.
In another embodiment, the semiconductor device structure includes a support region comprising a gate structure, source and drain regions adjacent to the gate structure, and a silicide layer disposed on the source and drain regions, wherein the gate structure comprises a dielectric capping layer, a metal conductor and a polysilicon layer; an array region comprising a plurality of embedded DRAM cells, a bitline diffusion region electrically connecting adjacent DRAM cells, an array gate stack structure, a polysilicon layer, wherein the polysilicon layer includes a silicide surface; an isolation region, wherein the isolation region electrically separates the support region from the array region; and an interconnect structure disposed on the isolation region comprising a polysilicon layer and a silicide layer formed on the polysilicon layer.
In another embodiment, the semiconductor device structure includes an active wordline comprising a first gate structure formed on a storage capacitor, wherein the first gate structure comprises a metal conductor layer, a dielectric capping layer and a spacer layer formed on a portion of the first gate structure; a passing wordline spaced apart from the active wordline, the passing wordline comprising a second gate structure, wherein the second gate structure comprises a metal conductor, a dielectric capping layer, an underlying oxide layer and a spacer layer formed on a portion of the second gate structure; a bitline diffusion region separating the active wordline from the passing wordline; and a landing pad comprising polysilicon having a silicide surface, wherein the landing pad is in contact with the first gate structure, the second gate structure and the bitline diffusion region.
In another embodiment, the semiconductor device structure includes an array region comprising a plurality of embedded DRAM cells, a bitline diffusion region electrically connecting adjacent DRAM cells, an array gate stack structure overlaying each DRAM cell, and a silicide polysilicon layer, wherein the gate structure comprises a metal conductor layer and a dielectric capping layer and wherein the silicide polysilicon layer is in contact with the bitline diffusion region and the dielectric capping layer; a support region comprising a polysilicon gate structure, a source and a drain region adjacent to the gate structure, and a silicide layer disposed on the gate structure and the source and drain regions; and an interconnect structure overlaying an isolation region, separating the support region from the array region, wherein the isolation region include a silicide polysilicon layer.
Advantageously, the process and structure eliminates the need for a M0 first metallization layer for sub-8F2 cells.
Other embodiments of the invention are contemplated to provide particular features and structural variants of the basic elements. The specific embodiments referred to as well as possible variations and the various features and advantages of the invention will become better understood when considered in connection with the accompanying drawings and detailed description that follows.